As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form the integrated circuits is increased, and the dimensions, sizes and spacings between the individual components or elements are reduced. While in the past such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having even smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between the conductors decreases, the resulting capacitance (a function of the dielectric constant (k) of the insulating material divided by the distance between conductive paths) increases. This increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, continual improvement in semiconductor IC performance and functionality is dependent upon developing materials that form a dielectric film with a lower dielectric constant (k) than that of the most commonly used material, silicon oxide, in order to reduce capacitance. As the dimensions of these devices get smaller and smaller, significant reduction in capacitance into the so-called “ultra low-k” regime is required.
New materials with low dielectric constants (known in the art as “low-k dielectrics”) are being investigated for use as insulators in semiconductor chip designs. A low dielectric constant material helps to enable further reductions in the integrated circuit feature dimensions. In conventional IC processing, SiO2 was used as a basis for the dielectric material, resulting in a dielectric constant of about 3.9. Advanced low-k dielectric materials have dielectric constants below about 2.7. The substance with the lowest dielectric constant is air (k=1.0). Therefore, porous dielectrics are very promising candidates, since they have the potential to provide very low dielectric constants.
However, porous films have shortcomings. Poor time-dependent dielectric breakdown (TDDB) performance has become a severe problem as a result of the seriously deteriorated barrier integrity. FIG. 1 illustrates a conventional interconnection formation scheme. A first copper line 4 is formed in a low-k dielectric layer 2. An etch stop layer 5 is formed on low-k dielectric layer 2. A second copper line 12 is electrically coupled to copper line 4 through a via 14. The second copper line 12 and via 14 are formed in a porous low-k dielectric layer 6. A diffusion barrier layer 10 is formed over sidewalls of the trench opening and via opening, in which copper is filled to form second copper line 12 and via 14. As low-k dielectric layer 6 is porous, the material in diffusion barrier layer 10 may penetrate into pores that are exposed on sidewalls of the via opening and trench opening, thus causing clouding effects, which will adversely affect the subsequent interconnection formation processes. To solve this problem, a dielectric pore sealing layer 8 is formed on exposed surfaces of low-k dielectric layer 6 in the trench and via openings to seal the pores. Dielectric pore sealing layer 8, however, typically has a higher k value than low-k dielectric layer 6 has. The RC delay in the interconnect structure is thus increased. In addition, the adhesion of dielectric pore sealing layer 8 and diffusion barrier layer 10 is not satisfactory, and delamination may occur in the subsequent chemical mechanical polish process. Furthermore, dielectric pore sealing layer 8 is not conductive, and thus the portion on an interface 16, which is exposed through the via opening, needs to be removed by an additional liner removal step.
Accordingly, a method that maximizes the benefit of low-k dielectrics while reducing the effects of their porous properties is needed.